The present invention relates to a metal oxide semiconductor (MOS) transistor, and more particularly, to a method of manufacturing a MOS transistor having a pocket structure which prevents substrate defects, due to ion-implantation, by forming a double shallow junction using an insulating film containing impurities.
As the integration of devices increases, short channel effects such as the punchthrough and drain induced barrier lowering (DIBL), are generated. In order to prevent the short channel effects, there was suggested a lightly doped drain (LDD) MOS transistor having an n.sup.- or p.sup.- type pocket region adjacent to source/drain regions of low concentration.
FIGS. 1A to 1D are cross-sectional views for showing a conventional method of manufacturing the LDD MOS transistor having the pocket region.
As shown in FIG. 1A, through the general process, a gate insulating film 12 and a gate 13 are sequentially formed on a silicon substrate 11.
As shown in FIG. 1B, using gate 13 as mask, an n.sup.- type impurity and a p.sup.- type impurity are sequentially ion-implanted in the substrate. Then, heat treatment is performed to activate the ion-implanted impurity, thereby forming low concentration n.sup.- type source/drain regions 14 and 15 having the double shallow junction and p.sup.- type pocket regions 16, respectively. At this time, low concentration n.sup.- type source/drain regions 14 and 15 having the double shallow junction are formed on both sides of the gate in the substrate, respectively. Further, p.sup.- type pocket regions 16 are formed so as to surround n.sup.- type source/drain regions 14 and 15, respectively.
As shown in FIG. 1C, a chemical vapor deposition (CVD) oxide film is deposited on the entire surface of the substrate. The oxide film is etched through the reactive ion etching (RIE) method, thereby forming sidewall spacers 17 on both sides of gate 13.
As shown in FIG. 1D, using sidewall spacers 17 and gate 13 as masks, an n.sup.+ type impurity is ion-implanted in the substrate. Then, heat treatment is performed to activate the ion-implanted impurity, thereby forming n.sup.+ type source/drain regions 18 and 19 of high concentration. As a result, the LDD MOS transistor having the pocket region is obtained.
According to the conventional method of manufacturing a MOS transistor, the general ion-implantation process or the tilt ion-implantation process is performed to form the source/drain regions and pocket region. However, if the above ion-implantation process is performed, the defect is generated in the channel region or junction of the silicon substrate. The defect serves as the leakage source of the junction, thereby deteriorating the device characteristics.